Accurate power estimation is an important problem in modern integrated circuits design. Currently, more than 60% of the dynamic power is consumed in the interconnect capacitances [1-4] due to the decreased gate load capacitances relative to the parasitic interconnect capacitances. Thus, accurate estimation of power dissipated in the interconnects is important. Previously, the parasitic capacitances of the interconnects to the ground were only considered. However, the parasitic coupling capacitances between interconnects are now growing more significant [5, 6]. Interconnect parasitic resistance and dimensions are currently the limiting factor of integration density [6]. With the progress of deep submicron technology, the aspect ratio of the interconnects increases significantly while the width and the spacing are reduced to allow low parasitic resistance while maintaining good integration density. With reduced width, the parasitic capacitance to ground decreases, and with reduced spacing, the parasitic coupling capacitance increases. As a result, the coupling capacitance is growing to dominate the total parasitic capacitance. In 90 nm technology, the ratio of parasitic coupling to ground capacitances of a typical interconnect is nearly 5.5. It is therefore evident that, with technology scaling, the component of power dissipation in parasitic coupling capacitances (coupling power) is becoming very significant.
Some approaches have been proposed to estimate the average power dissipation in digital circuits. However, prior work in power estimation has not considered coupling power estimation with detailed timing analysis. That is, the timing dependence of coupling power and the effects of relative switching delays have been ignored.
Therefore, a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies.